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for further information contact your local stmicroelectronics sales office. january 2013 doc id 024140 rev 1 1/11 11 STEVAL-ISA113V1 wide range single-output demonstration board based on the viper06hs data brief features universal input mains range: ? input voltage 90 - 265 v ac ? frequency 45 - 65 hz single-output voltage: 12 v at 0.35 a continuous operation standby mains consumption: < 30 mw at 230 v ac average efficiency: > 74% fully protected against faults (overload, feedback disconnection and overheating) emi: according to en55022-class-b rohs compliant description the STEVAL-ISA113V1 demonstration board is a 12 v-0.35 a power supply set in non-isolated flyback topology using the new viper06hs offline high-voltage converter by stmicroelectronics. the features of the device include an 800 v avalanche rugged power section, pwm operation at 115 khz with frequency jittering for lower emi, current limiting with adjustable set point, onboard soft-start, a safe auto-restart after a fault condition and a low standby power. the protection features available include a thermal shutdown with hysteresis, delayed overload protection, and open loop failure protection. s teval-i s a11 3 v1 www.st.com
adapter features STEVAL-ISA113V1 2/11 doc id 024140 rev 1 1 adapter features the electrical specifications are given in table 1 , the schematic in figure 1 , and the bill of material in table 2 . table 1. electrical specifications parameter symbol value input voltage range v in [90 v ac ; 265 v ac ] output voltage v out 12 v max. output current i out 0.35 a precision of output regulation v out_lf 5% high frequency output voltage ripple v out_hf 50 mv max. ambient operating temperature t amb 60 c table 2. bill of material ref. part description package manufacturer cin1 2.2 f, 400 v nhg series electrolytic capacitor cin2 4.7 f, 400 v ax series electrolytic capacitor saxon cvdd 1 f, 50 v electrolytic capacitor 1206 murata cfilt1 100 nf, 50 v ceramic capacitor 0805 cfilt2 not mounted cc 10 nf, 50 v ceramic capacitor 1206 cp 1 nf, 50 v ceramic capacitor 1206 cfb 1 nf, 50 v ceramic capacitor 0805 cout 330 f, 16 v zl series ultra-low esr electrolytic cap. rubycon d0 mb6s 600 v, 1 a diode bridge to-269aa vishay d2 stps2h100 100 v, 2 a power schottky rectifier sma st daux 1n4148w surface mount fast switching diode sod-123 zetex r0 4.7 3/4 w resistor rlim 15 k 5% 1/4 w resistor 0805 rc 47 k 5% 1/4 w resistor 0805 rfbh1 33 k 1% 1/4 w resistor 0805 rfbh2 0 1206 rfbl1 12 k 1% 1/4 w resistor 1206 rfbl2 0.47 k 1% 1/4 w resistor 0805
STEVAL-ISA113V1 adapter features doc id 024140 rev 1 3/11 the transformer core is a standard e13. the output voltage value is set in a simple way through the rfbh-rfbl voltage divider between the output terminal and the fb pin, according to the following formula: equation 1 in the schematic, rfbh has been split into rfbh1 and rfbh2; and rfbl into rfbl1 and rfbl2 in order to allow a better tuning of the output voltage value. if the jumper j1 is not selected, the ic is biased through the internal hv-startup current generator (?self-biasing?). if low standby consumption and good efficiency performance are required, the hv-startup current generator must be excluded. this can be done selecting the jumper j1, which connects the output terminal to the v dd pin through a small signal diode. the ic biasing through the output is referred to as ?external biasing?. ic1 viper06hs offline high-voltage pwm controller sso-10 st t1 1921.0040 transformer magnetica lin b82144a2105j 1 mh inductor lbc series epcos table 2. bill of material (continued) ref. part description package manufacturer ? ? ? ? ? ? ? ? + ? = rfbl rfbh v v out 1 3 . 3
adapter features STEVAL-ISA113V1 4/11 doc id 024140 rev 1 figure 1. application schematic d2 comp drain viper06 s h gnd fb lim vdd drain drain drain drain cf ilt2 j1 rf b h1 rf b l1 rf b l2 d au x rlim + cvdd cf ilt1 cf b cp rc cc + cin1 rf b h2 lin - + cin2 ac in vout + co u t t1 - + d0 r0 ac in am1 33 2 8 v1
STEVAL-ISA113V1 measurements doc id 024140 rev 1 5/11 2 measurements figure 2. line regulation at different loads: ic externally biased (j1 selected) figure 3. line regulation at different loads: ic self-biased (j1 not selected) am116 88 v1 11.7 11. 8 11.9 12 12.1 12.2 8 0 105 1 3 0 155 1 8 0 205 2 3 0 255 v out [v] v in [v ac ] 0 25 % 50 % 75 % 100 % am11691v1 11.7 11. 8 11.9 12 12.1 12.2 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 50.4 v out [v] i out [a] 90 115 2 3 0 265 figure 4. efficiency vs. v in ic externally biased (j1 selected) figure 5. efficiency vs. v in ic self-biased (j1 not selected) am11696v1 50 55 60 65 70 75 8 0 8 5 8 0 110 140 170 200 2 3 0 260 eff [ % ] v in [v ac ] 25 % 50 % 75 % 100 % am115 3 7v1 50 55 60 65 70 75 8 0 8 5 8 0 110 140 170 200 2 3 0 260 eff [ % ] v in [v ac ] 25 % 50 % 75 % 100 % figure 6. efficiency at different input voltages: ic externally biased (j1 selected) figure 7. efficiency at different input voltages: ic self-biased (j1 not selected) am116 3 2v1 am116 33 v1
measurements STEVAL-ISA113V1 6/11 doc id 024140 rev 1 figure 8. active mode efficiency vs. v in ic externally biased (j1selected) figure 9. active mode efficiency vs. v in ic self-biased (j1 not selected) am115 38 v1 60 65 70 75 8 0 8 5 8 0 110 140 170 200 2 3 0 260 eff [ % ] v in [v ac ] am115 3 9v1 60 65 70 75 8 0 8 5 8 0 110 140 170 200 2 3 0260 eff [ % ] v in [v ac ] figure 10. input voltage averaged efficiency vs. load ic externally biased (j1 selected) figure 11. input voltage averaged efficiency vs. load ic self-biased (j1 not selected) am11540v1 60 65 70 75 8 0 8 5 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 50.4 eff [ % ] i out [a] am11541v1 60 65 70 75 8 0 8 5 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 50.4 eff [ % ] i out [a ] figure 12. p in vs. v in at no load and light load: ic externally biased (j1 selected) figure 13. p in vs. v in at no load and light load: ic self-biased (j1 not selected) am1154 3 v1 0 50 100 150 200 8 01051 3 01551 8 02052 3 0255 p in [mw] v in [v ac ] 0 25mw 50mw am11544v1 0 50 100 150 200 250 3 00 3 50 400 8 01051 3 01551 8 02052 3 0255 p in [mw] v in [v ac ] 0 25mw 50mw
STEVAL-ISA113V1 measurements doc id 024140 rev 1 7/11 figure 14. efficiency at p in = 1 w: ic externally biased (j1 selected) figure 15. efficiency at p in = 1 w: ic self- biased (j1 not selected) am11545v1 40 45 50 55 60 65 70 75 8 0 8 0 110 140 170 200 2 3 0260 eff [ % ] v in [v ac ] am11546v1 3 5 40 45 50 55 60 65 70 75 8 0 8 0 110 140 170 200 2 3 0260 eff [ % ] v in [v ac ] figure 16. p in at p out = 250 mw: ic externally biased (j1 selected) figure 17. p in at p out = 250 mw: ic self- biased (j1 not selected) am1 3 10 8 v1 0.25 0. 3 0. 3 5 0.4 0.45 0.5 8 0 110 140 170 200 2 3 0260 p in [w] v in [v ac ] am1 3 10 8 v1 0.25 0. 3 0. 3 5 0.4 0.45 0.5 8 0 110 140 170 200 2 3 0260 p in [w] v in [v ac ] am1 3 109v1 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0. 8 8 0 110 140 170 200 2 3 0260 p in [w] v in [v ac ]
board layout STEVAL-ISA113V1 8/11 doc id 024140 rev 1 3 board layout figure 18. board layout - complete figure 19. board layout - top layer + top overlay am1 333 9v1 am1 33 40v1
STEVAL-ISA113V1 board layout doc id 024140 rev 1 9/11 figure 20. board layout - bottom layer + top overlay am1 33 41v1
revision history STEVAL-ISA113V1 10/11 doc id 024140 rev 1 4 revision history table 3. document revision history date revision changes 10-jan-2013 1 initial release.
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